1. Field of the Invention
The present invention relates to an electrically erasable programmable read only memory (EEPROM) and particularly relates to a non-volatile memory device which is appropriate for storing multi-state data and for improving the degree of integration.
2. Description of the Related Art
FIG. 1 is a simplified block diagram showing the configuration of an EEPROM of a conventional type.
Referring to the drawing, the configuration is explained in the following.
This EEPROM comprises a memory cell array 8 including a memory cell 7; an address buffer 14 to hold address data input from outside; an X decoder 16 which selects a word line 1 with a signal of the address buffer 14; a Y decoder 18 which selects transistors 20 and 22 in a Y gate circuit 12 with a signal of the address buffer 14; a control signal source 24 which controls storage operation; a read/write stand-by control circuit 26 which controls the preparation of read/write operation based on the control signal source 24; a write circuit 28 which generates a write signal; a read circuit 32 which generates a read signal; a booster circuit and a timer circuit 30 which generate a high voltage to be applied to the memory cell array 8 in response to a signal of the write circuit 28; a high voltage switch 10 for applying a high voltage to a selected word line 1; a column latch and a high voltage switch 9 which apply a high voltage to a bit line 6 and a control gate line 5 selected by the Y decoder 18 and latch the high voltage state; a control gate circuit 46 which controls the control gate line 5 based on a signal of the write circuit 28; a write driver circuit 48 which controls a voltage signal of a bit line 6 based on a signal of the write circuit 28; a sense amplifier 50 which amplifies the data of the selected bit line 6; an input/output buffer 34 which holds an input/output signal; an input buffer 36 which holds an input signal; an output buffer 38 which holds an output signal in response to the output data of the read circuit 32 and the sense amplifier 50.
In the figure, a configuration circuit of a 1 bit line memory cell 7 in the memory cell array 8 is shown. The description on the configuration is given in the following.
The bit line 6 to be connected to a transistor 22 in a Y gate circuit 12, is connected to the column latch and the high voltage switch 9; a transistor 2, a memory transistor 3 and a transistor 72 are connected in series between the above-mentioned junction point and ground potential. A control line 5 to be connected to a transistor 20 in the Y gate circuit 12 is connected to the column latch and the high voltage switch 9 and the junction point is connected to the control gate of the memory transistor 3 with a control gate line 54 through a transistor 4. The gate of the transistor 72 is connected to the write circuit 28 through a connecting line 70.
FIG. 2 is a circuit diagram around a memory transistor equivalent to 1 bit of an EEPROM of a conventional type.
In the figure, following components are connected in series between the sense amplifier 50 and ground potential (GRD): the transistor 22 included in the Y gate circuit 12, the transistor 2 to be selected by X decoder 16, the memory transistor 3 which selectively stores or subtracts an electric charge and the transistor 72 to be turned ON or OFF by the signal of the write circuit 28. A signal line 52 from the Y decoder 18 is connected to the gate of the transistor 22; a word line 1 to be connected to X decoder 16 is connected to the gate of the transistor 2; the memory transistor 3 includes a control gate 56 and a floating gate 58, and a control gate line 54 is connected to the control gate 56; a connecting line 70 from the write circuit 28 is connected to the transistor 72; a connecting line from the high voltage switch 9a is connected to the junction point of the transistor 22 and the transistor 2. The configuration of the high voltage switch 9a is shown as follows: a transistor Q.sub.3 and a condenser C.sub.1 are connected in series between the source voltage V.sub.pp and a boosted pulse signal .phi..sub.1 ; a transistor Q.sub.4 is connected between the junction point of the transistor Q.sub.3 and the condenser C.sub.1, and the junction point of the transistor 22 and the transistor 2 (node N1); the gate of the transistor Q.sub.3 is connected between the node N1 and the transistor Q.sub.4 ; the gate of the transistor Q.sub.4 is connected to a junction point between the transistor Q.sub.4 and a node N2.
Functions of the high voltage switch 9a are explained simply in the following. The source voltage V.sub.pp is applied to the node N2 when transistor Q.sub.3 is turned on, and further a voltage boosted by pulse .phi..sub.1 is superimposed at the node N2; by the application of the boosted voltage to the gate of the transistor Q.sub.4, the transistor Q.sub.4 is made conductive, and the boosted voltage is applied to the node N1. Thereby the boosted voltage is applied to a drain region of the memory transistor 3 through the transistor 2 which is turned ON by the selection of the word line 1.
FIG. 3 is a simplified sectional drawing around a memory transistor of a common EEPROM.
Following is the explanation of the configuration. An N.sup.+ drain diffusion region 78 and an N.sup.+ source diffusion region 76 are formed at predetermined distance on a main surface of a semiconductor substrate 74. On the upper part of the region of the semiconductor substrate 74 which is to be channel region between the source diffusion region 76 and the drain diffusion region 78, a floating gate 58 is formed through a gate oxide layer 82. A control gate 56 is formed on the floating gate 58 through a gate oxide layer 80. The control gate 56 and the floating gate 58 are deformed to be closer to the semiconductor substrate 74 in the upper part of the drain diffusion region 78 as shown in the figure. Thereby the thickness of a part between the floating gate 58 and the drain diffusion region 78 becomes thinner than the thickness of the gate oxide layer 82, and the part becomes a tunnel oxide layer 84.
Following is the explanation of the operation of an EEPROM.
At first, erasing operation is explained. A positive high voltage (V.sub.pp for example 20 V) is applied to the control gate 56 and ground potential is given to the drain diffusion region 78, the source diffusion region 76 and the semiconductor substrate 74. In this state, a potential (for example 14 V) is given to the floating gate 58, which is a potential divided proportional to the capacitance of each of the tunnel oxide layer 84, the gate oxide layer 80 and the gate oxide layer 82. Thereby an electric field of an intensity (14 MV/cm) of 14 V divided by the film thickness of the tunnel oxide layer 84, for example 100 .ANG., is applied to the tunnel oxide layer 84. Because of this, the electrons in the drain diffusion region are injected into the floating gate. 58 with the tunnel phenomenon caused by the electric field.
The write operation is explained in the following. A high voltage is applied to the drain diffusion region 78 (for example 20 V) and ground potential is given to the control gate 56 and the semiconductor substrate 74; when a transistor 72 connected to the source diffusion region is made to be OFF, the source diffusion region 76 is floated; in this state a high voltage in the opposite direction to that in the above erase operation is applied to the tunnel oxide layer 84; therefore the electrons in the floating gate 58 are transferred excessively into the drain diffusion region 78 through the tunnel oxide layer 84 by the high voltage and write operation is performed.
As described in the above, data can be stored by changing the conditions of electrons in the floating gate 58.
The read operation is explained in the following. Prescribed voltage (for example 1 V) is applied to the drain diffusion region 78 and the source diffusion 76 region is grounded; ground potential is given to the control gate 56. In this state, data can be read by detecting the current between the drain diffusion region 78 and the source diffusion region 76, the current which is generated or not by an electron holding condition in the floating gate 58.
FIG. 4 shows a gate voltage/drain current characteristic of a conventional EEPROM.
In the figure, the gate voltage of the control gate is taken on the axis of abscissa and the drain current generated between the drain diffusion region and the source region is taken on the axis of ordinate. The figure shows a characteristic when the voltage of the drain diffusion region is 1 V. A straight line 60 shows a state when write operation is performed, and the floating gate is in a state where electrons are excessively drawn out, so that a depletion type characteristic is shown. The threshold voltage of the depletion type transistor is -4 V. On the other hand, a straight line 64 shows a state where erase operation is performed; it shows a characteristic of an enhancement type because the floating gate is in a state where electrons are injected into it. The threshold voltage of the enhancement type transistor is 4 V. In the read operation ground potential will be given to the control gate, and the drain current in this state shall be compared with an "Isen", a certain sense level, for detecting the presence of data. The data can be discriminated by a sense amplifier in such a way that when the drain current is more than "Isen" the datum is judged as "0" and when the current is less than "Isen" the datum is judged as "1".
A memory transistor of an EEPROM of a conventional type is constituted as described in the above; the transistor can therefore store only two values, "1" or "0", that is a binary value, according to the electron holding condition of the floating gate. This is not advantageous to an EEPROM which is inferior in the degree of integration to a DRAM.
In the title "A Four-State EEPROM Using Floating-Gate Memory Cells" in IEEE JOURNAL OF SOLID-STATE CIRCUITS VOL. SC-22, NO. 3, June 1987, it is disclosed that the write depth of a memory transistor is controlled with an address signal and a clock signal, and data are read by discriminating the drain current based on the write depth. In this document, it is not mentioned about the method according to the present invention wherein the injection quantity of electric current into the floating gate is controlled by giving prescribed voltage to the source region, nor is mentioned about the exchange of data with peripheral units based on binary data.